We are looking for a Verification Engineer with 8-10 years of experience in verifying complex ICs. You will be involved in both chip-level and block/unit-level verification. Responsibilities also include chip level integration and IC backend support.

Requirements:
Defined and implemented RTL/gate level verification environments
Developed testbenches in Verilog and C PLI
Experienced with the formal verification, code coverage, and logic simulators

(i.e. NCVerilog, VCS).
Created and debugged tests for Verilog designs
Utilized scripting languages such as Perl and Tcl/Tk.
Knowledgable in IC development from netlist to masks (Verilog RTL, sythesis, static timing (constraints), floorplanning, BIST/SCAN insertion, power analysis, package design)
Networking experience is a plus.