Job Description:
Senior Digital IC Design Engineer

Location: Phoenix, Arizona

Position Summary:

• Senior ASIC Design Engineer needed to implement Digital functions within mixed signal ASICs.
• Initial tasking to be Real-Time Clocks, I2C Interface & Register Map, and CODEC integration.

Requirements:

• 10+ years in Digital Design, at least 5+ years in Verilog/Synthesis based ASIC Design.
• Verilog language & simulation verification experience.
• Mixed-signal simulation (Cadence AMS), interfacing with analog functions.
• Logic Synthesis & Static Timing Analysis.
• Design for test, scan insertion, ATPG, Functional Test Vectors.
• Interfacing with Place & Route, Back-annotated simulation verification.
• Taken at least 2 ASICs through entire flow of specification to prototypes.
• This individual must have the knowledge and capability to execute the entire design process without significant assistance, as most all other engineers at this location are analog designers.


Interested and qualified candidates please email your resume in MS Word format to:

Javier Leon
(858) 397-1667
javier@talentfuse.com
www.linkedin.com/in/javierleon (are we linked?)