Job Description:
Senior ASIC Design Engineer

Responsibilities:
The Senior ASIC Design Engineer position participates in the design of Kilocore ASIC products, including block-level design and micro-architecture. Specific responsibilities include:
Micro-architecture definition working closely with architects.
RTL Block-level design using Verilog.
Basic block-level verification.
Synthesis, including development of synthesis constraints.
Assists with floor-planning and timing closure.
Interfaces with back-end team to ensure correct implementation.

Qualifications:
Minimum BS EE/CS required, MS preferred, plus 10 or more years of relevant industry experience.
Experience with design of major portions of at least four successful ASIC/SoC designs, at least two in 90nm or 130nm technologies. Experience with graphics/media processors, reconfigurable processors, or microprocessors desirable.
Strong logic design, synthesis, functional and timing verification skills.
Very knowledgeable about industry-standard design tools, including simulators, formal tools, linters/RTL analysis tools, synthesis tools, static timing tools, placement and routing, DFT tools, etc.
Good programming skills, specifically Perl/Tcl scripting.
The ideal candidate will be familiar with all stages in the ASIC design flow including DFT, timing analysis, floor planning, ECO flow, silicon bring-up, and ATE test support.
Flexible, creative, and able to perform high quality work independently with minimal supervision.
Team player with excellent written and verbal communications skills.