Job Description:
ASIC Design/DFT Engineer

Responsibilities:
The ASIC Design/DFT Engineer position participates in the design of Kilocore ASIC products, with a focus on DFT. Specific responsibilities include:
DFT including Memory BIST, scan insertion, ATPG, JTAG, boundary scan.
Verification of DFT at RTL/gate levels using simulation.
Assists with synthesis, floor-planning, timing closure, and interface with back-end team, especially as related to DFT issues.
Assists with RTL Block-level design and verification using Verilog.

Qualifications:
Minimum BS EE/CS required, MS preferred, plus 7 or more years of relevant industry experience.
Experience with DFT for at least three successful ASIC/SoC designs, at least one in 90nm or 130nm technologies. Experience with graphics/media processors, reconfigurable processors, or microprocessors desirable.
Very knowledgeable about Design for Test concepts and proficient with DFT tools/methodology.
Strong logic design, synthesis, functional and timing verification skills.
Very knowledgeable about industry-standard design tools, including simulators, formal tools, linters/RTL analysis tools, synthesis tools, static timing tools, etc.
Good programming skills, specifically Perl/Tcl scripting.
Flexible, creative, and able to perform high quality work independently with minimal supervision.
Team player with excellent written and verbal communications skills.