Job Description:

Full Custom ASIC Design Engineer

As a Design Engineer, you will perform the design of high-speed digital integrated circuits using advanced CMOS process technology. You will be responsible for all HDL modeling ranging from behavioral concepts, down to the transistor level. You must own each design, taking it upon yourself to ensure it is correct and optimized, taking into account DFT and DFM.
Responsible for modeling right down to the transistor level. High involvement with verification, timing, test pattern generation, layout and back-end verification. Constant interaction with test engineering to anticipate testing issues, design for test concerns, and to facilitate silicon debug and characterization.

Responsibilities:
Own each block from concept to tape-out.
Develop behavioral, RTL, gate and transistor level models of logic blocks and memories, using Verilog.
Capable of verifying and simulating each said level of design abstraction, leading to full chip test and verification.
Responsible for timing closure of each block.
Analyze testability and implement solutions, such as scan chains and BIST.
Consistently meet deadlines and milestones.
Ability to develop vectors for fault coverage based on circuit design.
Transistor sizing using HSPICE.

Job Qualifications:
5+ years of design experience.
2+ years of verification experience.
Must be fluent in behavioral, RTL and gate-level Verilog.
Strong digital design skills.
Knowledge of memory design, JTAG, BIST and design-for-test.
Strong C/C++ abilities.
Extensive use of HSPICE for transistor level simulations.
MSEE preferred.