ASIC Design (Wireless)
| Job
code: |
5303 |
| Job Category: |
ASIC |
| City: |
MILPITAS |
Job Description:
Description of duties and responsibilities: The ASIC design engineer will be responsible for architecting, designing and coding RTL using Verilog for the PHY and MAC of the Baseband chips. The engineer will be performing simulations and verifications to ensure that his/her designs meet specifications. The engineer will be performing synthesis and post-layout simulations. Specifications must be generated before the design and also updated regularly. The ASIC design candidate should have at least 5 years of experiences in ASIC design and digital chip design. He/she should be familiar with Verilog and/or VHDL. Experiences in wireless and FPGA are preferred. In Depth Knowledge: - The ASIC design candidate should have at least 5 years of experiences in ASIC design and digital chip design. - He/she should be familiar with Verilog and/or VHDL. - Experiences in wireless and FPGA are preferred. - Knowledge and experience with WLAN, UWB, Bluetooth or other wireless technologies- Prefer to have experiences in designing OFDM, FFT and Viterbi decoderExperience Desired: - At least 5 years experience in ASIC design - Experiences in embedded ARM are preferredEducation: - BSEE is required. - MSEE is preferred
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