ASIC Design Engineer RTL
Job Description:
The ASIC Design Engineer RTL will be responsible for architecting, designing and coding RTL using Verilog for the PHY and MAC of the Baseband chips, and will be performing simulations and verifications to ensure that his/her designs meet specifications. The engineer will also be performing synthesis and post-layout simulations. Specifications must be generated before the design and also updated regularly.
Job Requirements :
The ASIC design candidate should have at least 5 years of experiences in ASIC design and digital chip design. He/she should be familiar with Verilog and/or VHDL. Experiences in wireless and FPGA are preferred. Knowledge and experience with WLAN, UWB, Bluetooth or other wireless technologies is a plus. Prefer to have experiences in designing OFDM, FFT and Viterbi decoder. Experiences in embedded ARM are also preferred.
BSEE is required. MSEE is preferred.