Job Description:

Senior Design Verification Engineer

Description:

Will be a leader of the team defining verification methodology, and verifying a high performance communications processor chip.

Responsibilities:

• Define verification architecture, methodology, and tools
• In-depth understanding of chip architecture and microarchitecture
• Develop test plans and write directed tests for new designs
• Selection and integration of verification IP
• Generate system & module level test benches, BFMs, transactors, & monitors
• Creation of internal verification tools
• Ownership of RTL and gate simulation environments
• Support silicon bring-up and production activities

Requirements:

• MS degree in EE, CS, or equivalent, with 10+ years relevant experience
• Highly motivated, results driven, with excellent communication skills
• Able to work both independently and as a team member
• Deep knowledge of ASIC verification flows and methodologies
• Familiar with Verilog simulators and PLI interface
• Experience with Verilog, C, assembly, UNIX scripting languages

Desirable Experience:

• Verification of I/O protocols such as PCI, PCIe, USB, Ethernet
• Familiar with processor architecture and microarchitecture
• System Verilog
• Formal Verification Methodology
• Assertion Verification Methodology
• Functional Coverage
• C++