ASIC PHYSICAL DESIGN VERIFICATION ENGINEER
Specific Responsibilities:
§ Responsible for physical design flows used in building our client's next generation ASIC's.
§ Responsible for review and integration of design rules, developing design flows supporting floorplanning, synthesis, place and route, as well as verification flows supporting timing.
§ Responsible for the physical Design layout and verification of the ASIC.
§ Design new techniques to improve the performance of the ASIC.
§ Work across organizational and geographic boundaries and interact
Qualifications and Experience:
§ BSEE is required, MSEE is preferred.
§ 2-5+ years experience as an ASIC or Integrated Circuit (IC) PDV Engineer.
§ Exposure to complete chip development lifecycle.
§ Understanding of HW/SW interaction and tradeoff.
§ Hands-on experience and in-depth knowledge of flows, parasitic-modeling, and commercial Electronic Design Automation (EDA) tools is required.
§ Understanding of Architectural CPU design flows and methodologies is a plus.
§ Knowledge of Calibre and Magma is required.
§ Strong skills in Perl, Tcl, C-Shell, floorplanning, place and route, LVS/DRC/RCE.
§ Strong presentation and communication skills.
§ Highly motivated, organized, and ethical.