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Responsible for analog circuit design, verification, layout and testing of a variety of blocks including very high speed, high linearity ADC, DAC and PLL
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Based on experience might be required to lead the design of a sub block and supervise a team of engineers
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Contribute to specifications of packaging, ESD and test development
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Comprehensive understanding of the principles of large-signal transistor level analog circuit design, particularly in CMOS
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Expert in state of the art tools and related work-flows commonly used for sub micron mixed signal design including experience with Matlab, Cadence design environment, Verilog A, and mixed mode simulations.
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Direct design experience in at least two of the following areas: High speed ADCs, DACs, switched capacitor filters, Line drivers, Programmable gain amplifiers, high performance Phase locked loops and power regulators
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Track record in successful complex analog silicon implementations involving one or more of the above areas.
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Excellent communication skills
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Design of Ethernet PHYs (10/100 or Gigabit) or DSL AFEs a plus
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Project leadership experience on successful complex analog chips a plus.
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RF experience at frequencies up to 1 GHz a plus