Job Description:

• Design and integrate IPs for SOC solutions using state of the art IC design flow
• Perform RTL coding
• Perform functional verification of design on block and IC level
• Generate test benches
• Perform synthesis and timing closure
• Support SCAN insertion and ATPG
• Provide design documentations for applications, test and customers
• Support and perform bench validation of prototype ASIC.
  

Education and Job Experience Requirements

• BSEE, MSEE preferred
• 3-4 years VHDL/Verilog coding and simulation experience a MUST
• 5+ years in an ASIC design environment
• Logic synthesis with Synopsys
• Experience in graphic controllers and display controllers a plus
• Experience with C/C++, PERL, Linux preferred
• Experience with mixed signal SOC preferred.