Position title: Senior Design Verification Engineer
Number of Open Positions: 7
Direct or contract position: Either
Detailed skills required: Verification engineer responsible for understanding the expected functionality of designs, developing corresponding testplans, designing and developing verification environment components, and applying these to verify complex designs. Solid OOPs programming skills and strong verification skills: test planning, problem solving and debug techniques are required. Prefer at least 5 years or more of direct, hands-on experience in chip/block verification
Specific tool experience required: Strong working knowledge of SystemVerilog and VMM, plus experience with VCS, C/C++, Tcl and Perl scripting.
Preferred Design Center location (include optional locations if appropriate): San Jose (on-site work in Cupertino)
Start date: Immediate
Expected duration (for contractor positions): At least 6 months
Salary range: DOE