Job Description:

Senior ASIC Design Engineer 

• RTL and digital circuit design, analyses, simulations and verification for deep sub-micron mixed-signal CMOS designs.
• Responsible for synthesis, timing analysis, power analysis, and post-layout simulation and verification.
• Evaluate designs trade-off and comparison analysis in all design aspects.
• Perform DFT and generate test vectors.

Minimum Requirements

• Five or more years in ASIC and digital design.
• Experiences with mixed-signal circuits designs.
• Familiar with Verilog and/or VHDL.
• Strong background in DSP, mathematical and electromagnetic theories.
• Solid understanding of ASIC design methodology from front-end to back-end.
• Experience with various EDA design, verification, and layout tools. Track record of quality designs with multiple complete design cycles.
• BSEE required. MSEE or Ph.D. EE preferred.

Applicable Skills:
RTL, CMOS, VERILOG, MIXED SIGNAL