Job Description:

Position title:  Senior DFT Engineer

Direct or contract position:  Either

Detailed skills required: 

Extensive experiences in the deployment and implementation of industry standard DFT techniques as pertaining to large complex ASICs that include:

• Full scan insertion of designs having multiple clock domains, debugging and diagnosing scan rule violations
• Automatic test pattern generation (ATPG) and test coverage improvement methods
• Memory BIST and Boundary scan logic (JTAG)
• Test pattern verification in various test modes
• Analyzing reports from DFT and STA tools
• Prefer at least 8 years or more of direct, hands-on experience in full chip DFT.

Specific tool experience required:  DFT Compiler, BSD Compiler, Tetramax, Logic Vision, VCS, Primetime.  Strong working knowledge of Perl, tcl, make, Linux/Unix shell script.

Preferred Design Center location:  San Diego

Applicable Skills:
DFT, TETRAMAX, JTAG