Job Description:

Position title:  Senior Design Verification Engineer

Direct or contract position:  Either

       Detailed skills required: 

• Verification engineer responsible for understanding the expected functionality of designs, developing corresponding testplans, designing and developing verification environment components, and applying these to verify complex designs.
• Verilog, SystemC, C++  experience required.  Solid OOPs programming skills and strong verification skills: test planning, problem solving and debug techniques are required.
• Prefer at least 5 years or more of direct, hands-on experience in chip/block verification

Specific tool experience required: 

         Working knowledge of Synchronous MultiProcessing (SMP) and cache coherency and experience with Hypertransport, 10G Ethernet or Infiniband preferred.   

Preferred Design Center location (include optional locations if appropriate):  San Jose (on-site work in the Bay Area)

Applicable Skills:
VERIFICATION, VERILOG, SystemC, SMP, HYPERTRANSPORT